Intel to increase L1 and L2 caches in Tiger Lake

Semiconductor manufacturer Intel Tiger Lake chips with the mobile wing layout is likely to change the layout. The chip on Geekbench seems to be quite muscular.


Intel to increase L1 and L2 caches in Tiger Lake

Semiconductor manufacturer Intel Tiger Lake chips with the mobile wing layout is likely to change the layout. The chip on Geekbench seems to be quite muscular.

Intel seems to be preparing to respond to AMD in the mobile market. The company, which previously increased the L1 and L2 caches on Sky Lake-X processors, is taking a similar move in the mobile market.

The L2 cache of the mobile Tiger Lake processor in Geekbench's database is 1.25 MB per core, totaling 5 MB . This corresponds to a 400% increase compared to the total 1 MB L2 cache of the existing chips. At the L1 level, the command memory has been upgraded to 48 KB, while the data cache remains 32 KB.

See Also "AMD's 4th generation Ryzen APU family has been codenamed"

Unlike Intel's improvement in Sky Lake-X , the 50% increase in contrast to the decrease in the L3 cache does not go unnoticed. Tiger Lake CPUs with a total of 12 MB of buffer memory is another highlight of the PCIe 4.0 support. Finally, the models expected to go through the 10 nm + process are expected to take their place on the first laptops in the period 2020-2021 .

Intel Tiger Lake CPU Architecture – Potential HEDT-Like 10nm Cache Rebalance Incoming


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